View X9400YV24M-27_3758281.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

xicor, inc. 2000 patents pending 7061-1.1 2/28/00 ep characteristics subject to change without notice 1 of 22 low noise/low power x9400 quad nonvolatile digitally controlled potentiometer features ? quad C four separate pots ? 64 resistor taps/pot ? spi serial interface ? wiper resistance, 150 w typical ? four non-volatile data registers for each pot ? non-volatile storage of wiper position ? standby current < 1 a max (total package) ?v cc = 2.7v to 5.5v operation v+ = 2.7v to 5.5v vC = C2.7v to C5.5v ? 10k w , 2.5k w total pot resistance ? 100 yr. data retention ? 24-lead soic, 24-lead tssop, and 24-lead xbga packages description the x9400 digital potentiometer contains 4 separate 10k w potentiometers with a digitally programmable wiper position to one of 64 taps on each pot. the wiper position is determined by a serial digital code that is received on the spi serial port that is common to all four ports. the 63 individual resistors in each pot are all equal creating a linear taper from one end of the pot to the other. there are also four 6 bit non-volatile data registers associated with each pot for storing system data and the most recent wiper position. powering up the device causes the contents of r 0 register of each pot to be loaded into the wiper counter register restoring the last known wiper position for each pot. functional diagram r0 r1 r2 r3 wiper counter register (wcr) resistor array vh1 vl1 r0 r1 r2 r3 wiper counter register (wcr) interf a ce and control circuitr y cs sck a0 a1 vh0 vl0 data 8 vw0 vw1 so si r0 r1 r2 r3 wiper counter register (wcr) resistor array pot2 vh2 vl2 vw2 r0 r1 r2 r3 wiper counter register (wcr) resistor array pot3 vh3 vl3 vw3 pot1 hold wp pot 0
x9400 characteristics subject to change without notice 2 of 22 pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9400. chip select (cs ) when cs is high, the x9400 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9400, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 C a 1 ) the address inputs are used to set the least signi?cant 2 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9400. a maximum of 4 devices may occupy the spi serial bus. potentiometer pins v h (v h0 C v h3 ), v l (v l0 C v l3 ) the vh and vl inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w (v w0 C v w3 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the wiper counter registers. analog supplies (v+, v-) the analog supplies v+, v- are the supply voltages for the eepot analog section. pin configuration vcc vl0 vh0 wp si a 1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v+ vl3 vh3 vw3 a 0 so hold sck vl2 vh2 dip/soic x9400 v ss vw0 14 13 11 12 cs vl1 vh1 vw1 vw2 v- si a 1 v l1 vC v w2 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 wp cs v w0 v h0 v l0 v cc v+ v l3 v h3 v w3 tssop x9400 hold v h1 14 13 11 12 v w1 v h2 v l2 sck a 0 so v ss 2 3 4 a b c d e f top viewCbumps down v w0 v l0 v+ a 0 hold v l1 v cc v l3 v w3 so si v w1 sck v l2 wp v- v h0 v h1 v h3 v h2 v ss v w2 cs a 1 1 xbga
x9400 characteristics subject to change without notice 3 of 22 pin names device description the x9400 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the eepot potentiometers. serial interface the x9400 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9400 is comprised of four resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?xed terminals of a mechanical potentiometer (v h and v l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. wiper counter register (wcr) the x9400 contains four wiper counter registers, one for each eepot potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register or global xfr data register instructions (parallel load); it can be modi?ed one step at a time by the increment/decrement instruction. finally, it is loaded with the contents of its data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9400 is powered-down. although the register is automatically loaded with the value in r0 upon power-up, this may be different from the value present at power-down. data registers each potentiometer has four 6-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. symbol description sck serial clock si, so serial data a 0 -a 1 device address v h0C v h3 , v l0C v l3 potentiometers (terminal equivalent) v w0C v w1 potentiometers (wiper equivalent) wp hardware write protection v+,v- analog and voltage follower supplies v cc system supply voltage vss system ground nc no connection table 1. data register detail (msb) (lsb) d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv
x9400 characteristics subject to change without notice 4 of 22 write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions identification (id) byte the ?rst byte sent to the x9400 from the host, following a cs going high to low, is called the identi?cation byte. the most signi?cant four bits of the slave address are a device type identi?er, for the x9400 this is ?xed as 0101[b] (refer to figure 2). the two least signi?cant bits in the id byte select one of four devices on the bus. the physical device address is de?ned by the state of the a 0 -a 1 input pins. the x9400 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9400 to successfully continue the command sequence. the a 0 Ca 1 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. figure 2. identi?cation byte format instruction byte the next byte sent to the x9400 contains the instruction and register pointer information. the four most signi?cant bits are the instruction. the next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. the format is shown below in figure 3. figure 3. instruction byte format 1 00 0 0 a1 a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 p1 p0 pot select register select instructions figure 1. detailed potentiometer block diagram serial data path fr om interf a ce circuitr y register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn v h v l v w 8 6 c o u n t e r d e c o d e if wcr = 00[h] then vw = vl if wcr = 3f[h] then vw = vh wiper (one of four arrays) (wcr)
x9400 characteristics subject to change without notice 5 of 22 the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits (p1 and p 0 ) selects which one of the four potentiometers is to be affected by the instruction. four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: ? xfr data register to wiper counter register - this transfers the contents of one speci?ed data register to the associated wiper counter register. ? xfr wiper counter register to data register - this transfers the contents of the speci?ed wiper counter register to the speci?ed associated data register. ? global xfr data register to wiper counter register - this transfers the contents of all speci?ed data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register - this transfers the contents of all wiper counter registers to the speci?ed associated data registers. the basic sequence of the two byte instructions is illustrated in figure 4. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9400; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? read wiper counter register - read the current wiper position of the selected pot, ?wr ite wiper counter register - change current wiper position of the selected pot, ? read data register - read the contents of the selected data register; ?wr ite data register - write a new value to the selected data register. ? read status - this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 5 and figure 6. the ?nal command is increment/decrement. it is different from the other commands, because its length is indeterminate. once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a ?ne tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 7 and figure 8.
x9400 characteristics subject to change without notice 6 of 22 figure 4. two-byte command sequence figure 5. three-byte command sequence (write) figure 6. three-byte command sequence (read) figure 7. increment/decrement command squence 010100a1a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 00 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si cs 00 s0 0 0 d5 d4 d3 d2 d1 d0 dont care 010100a1a0 i3 i2 i1 i0 0 p1 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs
x9400 characteristics subject to change without notice 7 of 22 figure 8. increment/decrement timing limits table 1. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 10010 0 p 1 p 0 read the contents of the wiper counter register pointed to by p 1 -p 0 write wiper counter register 10100 0 p 1 p 0 write new value to the wiper counter register pointed to by p 1 -p 0 read data register 1 0 1 1 r 1 r 0 p 1 p 0 read the contents of the data register pointed to by p 1 -p 0 and r 1 Cr 0 write data register 1 1 0 0 r 1 r 0 p 1 p 0 write new value to the data register pointed to by p 1 -p 0 and r 1 Cr 0 xfr data register to wiper counter register 1101 r 1 r 0 p 1 p 0 transfer the contents of the data register pointed to by r 1 Cr 0 to the wiper counter register pointed to by p 1 -p 0 xfr wiper counter register to data register 1110 r 1 r 0 p 1 p 0 transfer the contents of the wiper counter register pointed to by p 1 -p 0 to the register pointed to by r 1 Cr 0 global xfr data register to wiper counter register 0001 r 1 r 0 00 transfer the contents of all four data registers pointed to by r 1 Cr 0 to their respective wiper counter register global xfr wiper counter register to data register 1000 r 1 r 0 00 transfer the contents of all wiper counter registers to their respective data registers pointed to by r 1 Cr 0 increment/decrement wiper counter register 00100 0 p 1 p 0 enable increment/decrement of the wiper counter register pointed to by p 1 -p 0 read status (wip bit) 0 1010 0 0 1 read the status of the internal write cycle, by checking the wip bit. sck si v w inc/dec cmd issued t wrid voltage out
x9400 characteristics subject to change without notice 8 of 22 instruction format notes: (1) a1 ~ a0: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (2) i: stands for the increment operation, si held high during active sck phase (high). (3) d: stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9400 on so) cs rising edge 010100 a 1 a 0 100100 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 010100 a 1 a 0 101000 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9400 on so) cs rising edge 010100 a 1 a 0 1011 r 1 r 0 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 010100 a 1 a 0 1100 r 1 r 0 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 010100 a 1 a 0 1101 r 1 r 0 p 1 p 0
x9400 characteristics subject to change without notice 9 of 22 transfer wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) global transfer data register (dr) to wiper counter register (wcr) global transfer wiper counter register (wcr) to data register (dr) read status cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1110 r 1 r 0 p 1 p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 010100 a 1 a 0 0010xx p 1 p 0 i/ d i/ d .... i/ d i/ d cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100 a 1 a 0 0001 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1000 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode wiper addresses data byte (sent by x9400 on so) cs rising edge 010100 a 1 a 0 010100010000000 w i p
x9400 characteristics subject to change without notice 10 of 22 absolute maximum ratings temperature under bias .......................... C65 c to +135 c storage temperature ............................... C65 c to +150 c voltage on sck, scl or any address input with respect to v ss .................................... C1v to +7v voltage on v+ (referenced to v ss )................................10v voltage on v- (referenced to v ss ) ............................... -10v (v+) C (v-) ......................................................................12v any v h .............................................................................v+ any v l ...............................................................................v- lead temperature (soldering, 10 seconds) ..............300 c comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?cation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0 c +70 c industrial C40 c +85 c device supply voltage (v cc ) limits x9400 5v 10% x9400-2.7 2.7v to 5.5v analog characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot/63 or (v h C v l )/63, single pot symbol parameter limits test conditions min. typ. max. units r total end to end resistance C20 +20 % power rating 50 mw 25 c, each pot i w wiper current C3 +3 ma r w wiper resistance 150 250 w wiper current = 1ma vv+ voltage on v+ pin x9400 +4.5 +5.5 v x9400-2.7 +2.7 +5.5 vv- voltage on v- pin x9400 -5.5 -4.5 v x9400-2.7 -5.5 -2.7 v term voltage on any v h or v l pin v- v+ v noise -120 dbv ref: 1khz resolution 1.6 % absolute linearity (1) C1 +1 mi (3) v w(n)(actual) C v w(n)(expected) relative linearity (2) C0.2 +0.2 mi (3) v w(n + 1) C [v w(n) + mi ] temperature coefficient 300 ppm/ c
x9400 characteristics subject to change without notice 11 of 22 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 m a f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (nonvolatile write) 1ma f sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 m a sck = si = v ss , addr. = v ss i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage C0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. units minimum endurance 100,000 data changes per register data retention 100 years symbol test max. units test conditions c out (4) output capacitance (so) 8 pf v out = 0v c in (4) input capacitance (a0, a1, si, and sck) 6 pf v in = 0v symbol parameter min. max. units t pur (5) power-up to initiation of read operation 1 1 ms t puw (5) power-up to initiation of write operation 5 5 ms t r v cc (7) v cc power up ramp 0.2 50 v/msec a.c. test conditions notes: (4) this parameter is periodically sampled and not 100% tested (5) t pur and t puw are the delays required from the time the third (last) power supply (vcc, v+ or v-) is stable until the speci?c instruction can be issued. these parameters are periodically sampled and not 100% tested. (6) the power supply sequence should be v ss , v-, v cc , v+ with no slope reversals on v cc , (7) this is not a tested or guaranteed parameter and should be used as a guideline. equivalent a.c. load circuit i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 w 100pf sda output 2.7v 100pf
x9400 characteristics subject to change without notice 12 of 22 ac timing high-voltage write cycle timing symbol parameter min. max. units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 m s t fi si, sck, hold and cs input fall time 2 m s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 m s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms
x9400 characteristics subject to change without notice 13 of 22 eepot timing symbol table . symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 10 m s t wrl wiper response time after instruction issued (all load instructions) 10 m s t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 450 ns waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
x9400 characteristics subject to change without notice 14 of 22 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo
x9400 characteristics subject to change without notice 15 of 22 eepot timing (for all load instructions) eepot timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck si msb lsb vwx t wrl ... so high impedance ... cs sck so si addr t wrid high impedance vwx ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction)
x9400 characteristics subject to change without notice 16 of 22 applications information basic configurations of electronic potentiometers application circuits v r v w +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + C v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + C v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k w 10k w 10k w 10k w -12v +12v tl072 + C v s v o r 2 r 1 } }
x9400 characteristics subject to change without notice 17 of 22 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + C v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 p rc) + C v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + C v s function generator r 2 r 4 all r s = 10k w + C v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + C r 2 + C r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
x9400 characteristics subject to change without notice 18 of 22 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) ref. pin 1 index 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.530 (13.46) 0.080 (2.03) 0.065 (1.65) 0 15 24-lead plastic dual in-line package type p typ. 0.010 (0.25)
x9400 characteristics subject to change without notice 19 of 22 packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0 C 8 x 45
x9400 characteristics subject to change without notice 20 of 22 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail a .031 (.80) .041 (1.05) 0 C 8 .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x)
x9400 characteristics subject to change without notice 21 of 22 a b a d c f e 1234 b a d c f e 1 2 3 4 b top view (bump side down) side view (bump side down) bottom view (bump side up) c d e f k a j b note: drawing not to scale = die oridentation mark symbol millimeters inches min nom. max min nom. max package body dimension x a 2.575 2.605 2.635 0.10138 0.10256 0.10374 package body dimension y b 3.794 3.824 3.854 0.14937 0.15055 0.15173 package height c 0.697 0.750 0.763 0.02744 0.02674 0.03004 package body thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850 ball height e 0.253 0.273 0.293 0.00996 0.01075 0.01154 ball diameter f 0.360 0.374 0.388 0.01417 0.01472 0.01528 total ball count g 24 ball count x axis h 4 ball count y axis i 6 pins pitch xaxis j 0.5 pins pitch y axis k 0.5 edge to ball center (corner) distance along x l 0.523 0.553 0.583 0.02057 0.02175 0.02293 edge to ball center (corner) distance along y m 0.632 0.662 0.692 0.02488 0.02606 0.02724 l m 24-ball bga (x9400wc)
x9400 characteristics subject to change without notice 22 of 22 ordering information device v cc limits blank = 5v 10% C2.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c package s24 = 24-lead soic v24 = 24-lead tssop z24 = 24-lead xbga potentiometer organization pot 0 pot 1 pot 2 pot 3 w = 10k w 10k w 10k w 10k w y = 2.5k w 2.5k w 2.5k w 2.5k w x9400 p t v y part mark convention 24 lead xbga top mark x9400wz24i-2.7 xabm x9400wz24 xabn x9400yz24 xabz x9400yz24i-2.7 xaby limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023, 694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents a nd additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

▲Up To Search▲

Price & Availability of X9400YV24M-27

	To Download X9400YV24M-27 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .